Description
Total Points: 16 The goal of this assignment is to develop the a) schematic and b) state machine diagram for the caches you’ll be implementing in your project in Phase 2.3. All of the cache details are listed on the Cache Design Canvas page. Read it carefully before starting! As explained there, you will need to determine how your cache is arranged and functions before starting implementation. Draw out the state machine for your cache controller as this will be required to get it working correctly. You may implement either a Mealy or Moore machine though a Moore machine is recommended as it will likely be easier. Be forewarned that the resulting state machine will be relatively large so it is best to start early. If we have concerns about your design, we will ask you to setup an appointment to talk about your FSM design before the Phase 2.3 due date. Problem 1 [8 points] Create the schematic and state machine diagram for the direct-mapped caches you will initially be using in Phase 2.3. As explained above, your memory system schematic should show how the direct-mapped cache, cache controller, and four-bank memory modules are connected (NOTE: these are the modules you will eventually use inside mem_system.v in Phase 2.3). And the state machine diagram should show the various states necessary to correctly operate your cache and the transitions between those states. Problem 2 [8 points] Next, we will make our caches two-way set associative. Create the schematic and state machine diagram for a two-way set associative cache. If you do not need any changes to your state machine diagram from Problem 1, please submit the same state machine diagram for both problems.
